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NXP Semiconductors /LPC13xx /SYSCON /STARTAPRP0

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Interpret as STARTAPRP0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (APRPIO0_0)APRPIO0_0 0 (APRPIO0_1)APRPIO0_1 0 (APRPIO0_2)APRPIO0_2 0 (APRPIO0_3)APRPIO0_3 0 (APRPIO0_4)APRPIO0_4 0 (APRPIO0_5)APRPIO0_5 0 (APRPIO0_6)APRPIO0_6 0 (APRPIO0_7)APRPIO0_7 0 (APRPIO0_8)APRPIO0_8 0 (APRPIO0_9)APRPIO0_9 0 (APRPIO0_10)APRPIO0_10 0 (APRPIO0_11)APRPIO0_11 0 (APRPIO1_0)APRPIO1_0 0 (APRPIO1_1)APRPIO1_1 0 (APRPIO1_2)APRPIO1_2 0 (APRPIO1_3)APRPIO1_3 0 (APRPIO1_4)APRPIO1_4 0 (APRPIO1_5)APRPIO1_5 0 (APRPIO1_6)APRPIO1_6 0 (APRPIO1_7)APRPIO1_7 0 (APRPIO1_8)APRPIO1_8 0 (APRPIO1_9)APRPIO1_9 0 (APRPIO1_10)APRPIO1_10 0 (APRPIO1_11)APRPIO1_11 0 (APRPIO2_0)APRPIO2_0 0 (APRPIO2_1)APRPIO2_1 0 (APRPIO2_2)APRPIO2_2 0 (APRPIO2_3)APRPIO2_3 0 (APRPIO2_4)APRPIO2_4 0 (APRPIO2_5)APRPIO2_5 0 (APRPIO2_6)APRPIO2_6 0 (APRPIO2_7)APRPIO2_7

Description

Start logic edge control register 0; bottom 32 interrupts

Fields

APRPIO0_0

Edge select for start logic input PIO0_n (bit 0 = PIO0_1, …, bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge.
APRPIO0_1

Edge select for start logic input PIO0_n (bit 0 = PIO0_1, …, bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge.
APRPIO0_2

Edge select for start logic input PIO0_n (bit 0 = PIO0_1, …, bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge.
APRPIO0_3

Edge select for start logic input PIO0_n (bit 0 = PIO0_1, …, bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge.
APRPIO0_4

Edge select for start logic input PIO0_n (bit 0 = PIO0_1, …, bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge.
APRPIO0_5

Edge select for start logic input PIO0_n (bit 0 = PIO0_1, …, bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge.
APRPIO0_6

Edge select for start logic input PIO0_n (bit 0 = PIO0_1, …, bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge.
APRPIO0_7

Edge select for start logic input PIO0_n (bit 0 = PIO0_1, …, bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge.
APRPIO0_8

Edge select for start logic input PIO0_n (bit 0 = PIO0_1, …, bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge.
APRPIO0_9

Edge select for start logic input PIO0_n (bit 0 = PIO0_1, …, bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge.
APRPIO0_10

Edge select for start logic input PIO0_n (bit 0 = PIO0_1, …, bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge.
APRPIO0_11

Edge select for start logic input PIO0_n (bit 0 = PIO0_1, …, bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge.
APRPIO1_0

Edge select for start logic input PIO1_n (bit 12 = PIO1_0, …, bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge.
APRPIO1_1

Edge select for start logic input PIO1_n (bit 12 = PIO1_0, …, bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge.
APRPIO1_2

Edge select for start logic input PIO1_n (bit 12 = PIO1_0, …, bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge.
APRPIO1_3

Edge select for start logic input PIO1_n (bit 12 = PIO1_0, …, bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge.
APRPIO1_4

Edge select for start logic input PIO1_n (bit 12 = PIO1_0, …, bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge.
APRPIO1_5

Edge select for start logic input PIO1_n (bit 12 = PIO1_0, …, bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge.
APRPIO1_6

Edge select for start logic input PIO1_n (bit 12 = PIO1_0, …, bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge.
APRPIO1_7

Edge select for start logic input PIO1_n (bit 12 = PIO1_0, …, bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge.
APRPIO1_8

Edge select for start logic input PIO1_n (bit 12 = PIO1_0, …, bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge.
APRPIO1_9

Edge select for start logic input PIO1_n (bit 12 = PIO1_0, …, bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge.
APRPIO1_10

Edge select for start logic input PIO1_n (bit 12 = PIO1_0, …, bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge.
APRPIO1_11

Edge select for start logic input PIO1_n (bit 12 = PIO1_0, …, bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge.
APRPIO2_0

Edge select for start logic input PIO2_n (bit 24 = PIO2_0, …, bit 31 = PIO2_7). 0 = Falling edge. 1 = Rising edge.
APRPIO2_1

Edge select for start logic input PIO2_n (bit 24 = PIO2_0, …, bit 31 = PIO2_7). 0 = Falling edge. 1 = Rising edge.
APRPIO2_2

Edge select for start logic input PIO2_n (bit 24 = PIO2_0, …, bit 31 = PIO2_7). 0 = Falling edge. 1 = Rising edge.
APRPIO2_3

Edge select for start logic input PIO2_n (bit 24 = PIO2_0, …, bit 31 = PIO2_7). 0 = Falling edge. 1 = Rising edge.
APRPIO2_4

Edge select for start logic input PIO2_n (bit 24 = PIO2_0, …, bit 31 = PIO2_7). 0 = Falling edge. 1 = Rising edge.
APRPIO2_5

Edge select for start logic input PIO2_n (bit 24 = PIO2_0, …, bit 31 = PIO2_7). 0 = Falling edge. 1 = Rising edge.
APRPIO2_6

Edge select for start logic input PIO2_n (bit 24 = PIO2_0, …, bit 31 = PIO2_7). 0 = Falling edge. 1 = Rising edge.
APRPIO2_7

Edge select for start logic input PIO2_n (bit 24 = PIO2_0, …, bit 31 = PIO2_7). 0 = Falling edge. 1 = Rising edge.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data